Journal of Electrical & Electronic Systems

Shaktisinh Karnubha Jadeja

Publications

• Research Article
  Analysis of Power Reduction Techniques used in Testing of VLSI Circuits
  Author(s): Shaktisinh Karnubha Jadeja, Rajendra Patel and Jayesh PopatShaktisinh Karnubha Jadeja, Rajendra Patel and Jayesh Popat
  
  One of the most important parameter over the past decade in VLSI design is the Power dissipation during manufacturing test, as the circuit consume much more power during test than functional mode of operation. This paper presents analysis of low power testing techniques by which Power optimized test patterns are obtained. The compaction technique has been validated using benchmark examples, and it has been shown that average 33% of test patterns have been reduced by which power is minimized. Evaluation of various techniques under consideration in this paper is carried out by open source tool ATALANTA for test pattern generation and MATLAB for optimization... Read More»
  DOI: 10.4172/2332-0796.1000148

  Abstract PDF