alexa Upasna Vishnoi | RWTH Aachen University
ISSN: 2332-0796

Journal of Electrical & Electronic Systems
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Upasna Vishnoi

Upasna Vishnoi Upasna Vishnoi
Data Storage IC R&D Marvell Semiconductor Inc,
United States Headquarters,
Santa Clara, USA
Biography

Dr. -Ing. Upasna Vishnoi works as a Senior Digital Design Engineer in Data Storage IC R&D at Marvell Semiconductor Inc. headquartered in Santa Clara, CA, USA. She was awarded Doctor of Engineering degree from the Institute of Electrical Engineering and Computer Systems at University of Technology RWTH Aachen, Germany in 2016. During her Ph.D. she was involved in research activities on VLSI architectural strategies for highly Area- and Energy-Efficient QR-Decomposition CMOS Macros for a wide range of applications to be implemented in deep-sub-micron CMOS technologies. During that time she published several research papers, delivered invited talks and received a PhD Forum Best Presentation Award. She received Master of Technology degree in Electronics Engineering (VLSI Design) in 2009 and Bachelors of Technology in Electronics and Instrumentation Engineering in 2007 from India. She is a Technical Program Committee member of several IEEE international conferences.

Research Interest

VLSI Architectural strategies for Energy- and Area-Efficient Digital Circuits for High-Throughput Applications, Cross-Layer Design Space Exploration over Architecture, Micro-Architecture and Circuit Level

Publications

Quantitative Optimization of Highly Efficient Dedicated CORDIC Macros for SoCs in Deep-Submicron CMOS Technologies
Upasna Vishnoi and Tobias G Noll
Review Article: J Electr Electron Syst 2017, 6:238
DOI: 10.4172/2332-0796.1000238
 
Highly-Flexible and Optimized, Area: and Energy-Efficient Matrix Decomposition Accelerators based on Givens Algorithms and CORDIC Rotations
Upasna Vishnoi and Tobias G Noll
Opinion Article: J Electr Electron Syst 2017, 6:231
DOI: 10.4172/2332-0796.1000231
 
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