Implementation of a New Compact Inverter Structure Controlled by Numeric Sinusoidal Pulse Width Modulation for Photovoltaic Applications

Copyright: © 2016 Abounada A, et al. This is an open-access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited. Implementation of a New Compact Inverter Structure Controlled by Numeric Sinusoidal Pulse Width Modulation for Photovoltaic Applications


Introduction
Energy crises and environmental pollution caused by consumption of traditional energy sources lead scientists to think about renewable energies to satisfy the world needs of electricity [1]. So, nowadays renewable energies are the most important subjects that researches and studies discuss [2]. Among these energy types, the solar is predicted to cover the maximum need of energy in the future [3]. Thus, a lot of articles present different photovoltaic systems structures [2,4,5], which are based on many power processing stages. This paper will focus on the inverter stage and its command. The structure presented here is very recent and understudied; it allows a conversion in a single stage with AC output voltage higher than the input voltage [6]. It is the boost inverter. The inverter supply is provided by three series batteries of 24 V. Thus, the inverter is powered by 72 V. The inverter output is modulated by a digital sinusoidal pulse width modulation SPWM inspired from the analogical one.
To give more details on this structure, this paper will contain in the first part the construction of the inverter, its principle of operating, and a simulation which interpret its performance. In the second part, the experimental study is presented to prove simulation results.

System Description
The boost inverter discussed here allows producing a filtered and amplified alternative voltage. It contains two bidirectional boost converters connected deferentially to a load [6,7]. Controlled by sinusoidal pulse width modulation SPWM command, each converter produces a DC voltage and an alternative component. The alternative components are sinusoidal signals and in phase opposition, whereas the DC components have the same value. This structure is shown by Figure 1 [8].

( )
The output voltage of the inverter is in "Eq. (3)" In order to explain the functioning of this inverter, we will consider one converter as shown in Figure 2 [9,10]: The functioning of the converter is divided into two parts: [0, d*T c3 ]: The switch M 3 is closed while M 4 is open, I l3 increases linearly, D 4 is reverse polarized, C 3 provides the load with energy, which decreases V 01 .
[d*T c3, T c3 ]: The switch M 4 is closed while M 3 is open, C 3 is charging by I l3 . So, the voltage V 01 increases [9,10].

Abstract
In order to cover energy requirement, the photovoltaic is one of the proposed solutions. However, according to the aim of its utilization, the direct current output voltage of photovoltaic source should be adjusted. The boost inverter is a recent power processing stage that can increase, filter and alternate direct current input voltage. So as to control it, there are various modulation types. Among them, the sinusoidal pulse width modulation is presented in a new digital form. The operating principle of the aforementioned inverter and command have been analyzed and verified by simulation and realization. Furthermore, frequency analysis of output voltage signal proves efficient results. It applies the same concept which is logic comparison of a sinusoidal wave to another triangular. So as to command the interrupters, we make use of the intersections of these signals [11][12][13].
As Figure 3 presents, the triangular signal is produced by a binary counter. It counts till a maximum value, stored in a register, then counts down until a minimal value. The sinusoidal one is represented by a table of values obtained by sampling a sinusoidal signal; this table is stored in a memory. The period of sampling is the same as commutation period of the inverter, which is equal to the period of the triangular signal elaborated by the counter.
In each period of sinusoidal signal, a software comparison between these two signals is done so as to produce an impulsion in higher or lower state.
The sinusoidal signal period gives suit of periodic impulsions modeled in width according to a sinusoidal law.
The numeric command SPWM is implemented in the microcontroller 16 F876 (20 MHz). The resulted SPWM signal should command MOSFET transistors. Since the intensity and the amplitude of this signal are unable to commutate the MOSFET, we added a driver between the microcontroller and the transistors. It is IR2111 circuit.
We can also produce the timing sequence by Excel software or Matlab and store it on the chip. This will allow us to optimize the chip performance.
Finally, in order to protect the microcontroller we added an optocoupler before the driver.
The circuit which produces the SPWM signals is presented in Figure 4.

Simulation
This part present a simulation of the inverter structure and its command discussed in the beginning under a power of 300 W. The inverter characteristics simulated are: Inductor: 0.23 µH, The capacitor: 260 µF, MOSFET: W45NM50 (Table 1).
The following Figures 5-10 show the realized inverter circuit in Orcade software and its simulation results: According to the simulation results, the output voltage waveforms are sinusoidal; they have a frequency of 50 Hz and amplitude of 110 V.

Realization
After verification and validation by simulation, now we present a practical implementation of the realized inverter structure and its command.
Where d is the duty cycle, Tc is the switching period When one converter is in boost operating the other should be in buck operating. The average voltage's expression for the first converter [11] is in Eq. (4) while that of the second is corresponding to Eq. (5): Then the transfer function can be concluded in Eq.
A linearization of this equation around d 0 gives "Eq. (8)": If we consider that V 0 is sinusoidal we will have "Eq. (9)" Where f is the frequency This equation presents the duty cycle's variation near to d 0 . To elaborate the command SPWM, in order to have a sinusoidal V 0, we will use the aforementioned "Eq. (9)".

The Digital Sinusoidal Pulse Width Modulation
To produce a sinusoidal voltage using this inverter, we command it with a digital modulation SPWM inspired from the analogical one.

Inverter
In Figure 11 below shows the fabricated inverter.
The command card: The control card is built with the microcontroller PIC16F876 and three circuits. They are used for isolation, adaptation and interfacing with the microcomputer. This card has two inputs and five outputs, four of them are used to command the switches of the inverter.
In Figure 12 below shows the realized command card.
The microcontroller chosen to implement the SPWM technique has two PWM outputs and a memory. The outputs generate the SPWM signal whereas the memory accommodates the program. The maximum clock frequency that the microcontroller can accept is 20 MHz. The implementation of the mechanism SPWM in the microcontroller goes through three steps: Firstly, a configuration in pulse with modulation mode of two outputs "CCP1" and "CCP2" should be done.
Secondly, the period T C3 of PWM signals is defined according to "Eq. (10)": 3 2 ( 1) Where the period of the oscillator is T osc , the predivisor of timer 2 is T p and PR 2 is a register. In order to fix the T C3 value to a required one, we should load the register PR 2 by a decimal value from "0" to "255".
Thirdly, the values K i , which give the duty cycles D i of number n, will be stored in a table and then loaded periodically according to a repetitive process. The loading procedure will be done by a timekeeper; it can belong to one of registers CCPR1L or CCPR2L according to "Eq. (11)" or "Eq. (12)".
( 1 ) OSC P CCPR L T T × × (11) ( 2 ) OSC P CCPR L T T × × Depending on "Eq. (13)", the generation of table's values K i can be done by using a software tool. Which help to obtain the duty cycle D i depending on "Eq. (14)".
The value of i goes from 1 until n The constants B, A and n will be determined as described subsequently.
The number n presents the number of duty cycles. It's given by the report T c3 /T r . 500V 250V 0V 0s 50ms 100ms      To choose A and B, on the one hand, we should consider the size of both registers CCPR1L and CCPR2L of 8 bits, thus these constants are positive and decimal. On the other hand, they will be chosen in order to have the duty cycle value equal to 50% for t=0, equal to 95% for t=T r /4 and equal to 5% for t=3 T r /4. The maximum duty cycle value 95% is obtained by "Eq. (15)": That will help to conclude the value of B+A As the duty cycle value 50% is obtained depending on "Eq. (16)": The value of B and then that of A will be easily deduced.
The implanted SPWM program undergoes from an interruption. This made the two values Ki and 255-Ki read and loaded simultaneously in both registers CCPR1L and CCPR2L. Then during every period T C3, two complementary motives SPWM are produced. This is caused by the over follow of timer 2. So we obtain the two desired signals SPWM during the period T r .
The value of B and then that of A will be easily deduced.
The implanted SPWM program undergoes from an interruption. This made the two values Ki and 255-Ki read and loaded simultaneously in both registers CCPR1L and CCPR2L. Then during every period T C3, two complementary motives SPWM are produced. This is caused by the over follow of timer 2. So we obtain the two desired signals SPWM during the period T r .

Experimental results
The output differential voltage of the realized boost inverter, applied on a resistive load, a capacitive load and inductive load, is presented in Figures 13-15.
These results show an output voltage highly near to be sinusoidal. It has a frequency of 59.94, a RMS voltage of 110.

Frequency analysis
Applying Fast Fourier Transform FFT on the inverter output voltage of every loads type offer various characteristics which are illustrated in Figure 16.
The fundamental has amplitude of 110 V; the 3 rd harmonics remains the most dominant with low amplitude of 3.32 V. This value can be negligible compared to the amplitude of the fundamental.    Practical results obtained show a favorable functioning of this inverter; its yield can be improved by an optimal choice of the interrupters used to establish it.

Conclusion
In this paper we have established and evaluated a new inverter structure which allows boosting, undulating and filtering a DC voltage in a single stage.