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ISSN: 2332-0796
Journal of Electrical & Electronic Systems
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Time Synchronization Mechanism for Radio Interferometer Array

El Houssain Ait Mansour1*, Bruno Da Silva2 and Karl-Ludwig Klein3

1Laboratoire d’´etudes spatiales, et d’instrumentation en, astrophysique – LESIA, 18330 Nanc¸ay, France

2St´ephane Bosse, Station de radioastronomie de Nanc¸ay, Route de souesmes, 18330 Nanc¸ay, France

3Observatoire de Paris, LESIA, LESIA - Bat 14, 92195 Meudon, France

*Corresponding Author:
El Houssain Ait Mansour
Department of Electronics
Observatoire de Paris/Station
de Rasdioastronomie de Nançay, France
Tel: +33(0)2 48 51 82 41
E-mail: [email protected]

Received Date: July 07, 2017; Accepted Date: July 20, 2017; Published Date: July 26, 2017

Citation: Mansour EHA, Silva BD, Klein KL (2017) Time Synchronization Mechanism for Radio Interferometer Array. J Electr Electron Syst 6: 230. doi: 10.4172/2332-0796.1000230

Copyright: © 2017 Mansour EHA, et al. This is an open-access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.

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Abstract

In both wired and wireless networks, synchronization is an important service for a wide range of applications in distributed systems. This includes radio interferometry. However, literature researches show that many distributed protocols cannot satisfy sub-ns time synchronization accuracy due to asymmetric delay errors, accumulated jitters and because of the strategy used to adjust offsets. This paper proposes a global time synchronization algorithm in distributed networks. The algorithm allows us to minimize asymmetric delays with sub-ns accuracy better than 10ps and achieved global time synchronization. The theory of the algorithm used is presented and analysed to prove that it achieves global time synchronization. Simulation results are given to show the performance and limitations of the proposed algorithm.

Keywords

Time synchronization; Algorithm; Asymmetric delay; Adjustment; Sub-ns; Accuracy

Introduction

Time synchronization is a critical problem for infrastructure in any distributed networks including radio interferometer [1]. Many global time synchronization algorithms were developed previously, but few of them can reach sub-ns accuracy in the distributed networks [2-5]. Additionally, several system issues limit the accuracy, such as asymmetric delays, long propagation delays, number of nodes and other sources of delay causes by measurement method.

The Nanc¸ay Heliograph (RH) Radio [6] is an analog radio interferometer array that consists of 48 distributed antennas, It allows one to construct radio images of the solar corona in the 150-450 MHz frequency band [7]. The Radio Frequency (RF) signals are transported in coaxial cables with different lengths (50-3.2 km) from the antenna to the receiver. The main limitations of the current instrument are offset delays errors introduced by manual calibration between each antenna and receiver. Furthermore, the switching time between each frequency analysed introduce a latency in solar images, also reduces the signal-to-noise ratio. In order to increase radio image resolution and data processing flexibility, a new study has started on a digital radio interferometer system. It requires a 1 GHz Analog-to-Digital Converter (ADC) frequency clock for each antenna (full band sampling). The new system enables one to acquire simultaneously radio images [8] at different frequencies with adjustable resolution. The main problems of this system are: the distribution of the high-frequency clock required for each antenna, the different lengths of cables between individual antennas and receiver, which need global time synchronization with sub-ns accuracy. The main objective of this paper is to reach a subns global time synchronization of a radio interferometer array as the Nanc¸ay Radioheliograph. This work is presented with these following steps:

• We propose an algorithm based on the computation of global delay offsets and the theory of global time synchronization adjustment in a distributed network (section III.A).

• We present iterative algorithm with generic implementation to compensate random asymmetric delays between master and slaves based on errors estimation and minimization (section III.B).

• We test the algorithm using measurements from the previous work on a distributed network with cables of lengths up to 3.2 km with different asymmetric delays. The performance and limitations of the algorithm are discussed (section IV).

Synchronization Protocols and Limitations

In distributed networks, physical clock drifts, temperature changing and measurements errors may reduce synchronization accuracy [9]. Identically, networks topology affects slightly synchronization accuracy. However, mean errors increase rapidly with number of nodes [5]. The biggest source of offset and jitter errors in synchronization algorithm systems from random delays between master AND slaves [10]. Offset delays estimation accuracy is important issue in time synchronization system [3]. The most important sources are the following:

• Send time: The time it takes the Master to construct a message

• Access time: Time delay to access to channel

• Propagation delay: Time delay between Master and slave, on the length of the connection

• Receiver time: Time it takes the slave to receive messages.

Most time synchronization protocols proved global time synchronization over Ethernet. They estimated and calibrated non deterministic sources of delays, mean offsets and jitters estimation with manual adjustment can increase PTP accuracy to sub-μs Equation [3]. Using precision PHTER, PTP protocol may achieved nanosecond software accuracy and sub-ns hardware accuracy (PPS) between master and slave clock [11]. Table 1 illustrates existing time synchronization protocols accuracy and implementation complexity.

Protocols Accuracy Layer Implementation
NTP [12] us 3 Complex
PTP [4,9,17] ns 2 Complex
PPS [11] ns 2 Complex
DTP [10] ns 2 Complex
GPS [10] ns 2 Complex
WR [15,16] sub-ns 1-2 Complex

Table 1: Existing time synchronization protocols accuracy and implementation complexity.

Full Synchronization Algorithm

Offsets compensation

In this section we present the main contributions of this paper. We describe the proposed algorithm for global time synchronization based on the previous researches in distributed networks. Consider an interferometer array with N antennas (i=1, 2,..., N), where each antenna (i.e., each slave) has round trip delay Equation (Figure 1) [12].

electrical-electronic-systems-delays-architecture

Figure 1: Delays architecture between Master and Slaves.

Equation(1)

Eq. (1) presents basic model delay between Master and Slave, Equation includes transmission delay, channel delay and reception delay, and so does Equation. Consider two slaves (i, i+1). Here we make assumptions; we neglected asymmetric delays between master and slave Equation. Additionally, Master to Master delays assumed different for each slave Equation. Let Ti be the delays between master and slave before offset delays compensation and:

Equation (2)

Let Equation be the delays between master and slave after offsets compensation. The average between each delay pair Equation and Equation is given by Eq. (3).

Equation (3)

For global synchronization, it is necessary to set to zero time difference between each slave pair, the synchronization condition is Equation Eq. (4)-(8) shows how to synchronize between antennas pairs (1,2).

Equation (4)

Equation(5)

Let’s insert two unknown offsets δx1 and δx2 between Master and pair antennas (1,2), then :

Equation (6)

Equation (7)

Equation (8)

Offsets compensation vector for N antennas is given by Eq. (9):

Equation (9)

In the offset delays compensation process, we introduced Equation in the path of the slave clocks. According to the assumption (symmetric delays), all clocks arrive simultaneously at the slave side Equation (Figure 2).

electrical-electronic-systems-offset-compensation

Figure 2: Offset delays compensation time diagram between Master and slaves.

Asymmetric delay error calibration

In this section we present an iterative algorithm to compute offsets vector (9). This algorithm enables us to reach global time synchronization in distributed networks. Here we make assumptions; we considered asymmetric delays between master and slave Eq. (10).

Equation(10)

Let μ and Min in be the adjustable parameters. Let Equation defines master to slave delay and round trip delay after calibration. Where Equation present ascending sort delays vector (Figure 1) allows to get a positive difference delay between each slave pairs (i,i+1) (ΔT(i)>0) (Figure 3). In the offsets calibration step in the algorithm, the last slave set as reference (slave with maximum round trip delay) (δx(N) set to 0) (Figure 3).

electrical-electronic-systems-pseudo-code-global

Figure 3: Pseudo-code for global synchronization algorithm include asymmetric delay calibration between master and slave.

Let Min define synchronization accuracy and μ define algorithm step-size. Values of the two factors affect directly the convergence or divergence and synchronization period (TSync) to achieve the required accuracy (time convergence). For each iteration, the proposed algorithm estimate global mean error for all slaves after offsets calibration (μe) (Eq. (11)). This error is due to asymmetric delays between master and slaves. When the required accuracy is not reached, the algorithm updates dMM according to Eq. (12).

Equation (11)

Equation(12)

Results and Discussions

In the previous sections we proposed global time synchronization theory and a possible implementation. We now proceed to evaluate the performance of proposed algorithm and limitations in radio interferometer array. Algorithm delay parameters had chosen [13].

Consider the interferometer array with N antennas with star topology sketched in Figure 4. The 1550 ns and 1390 ns fiber optics link are used between master and each slave. Let Li be the length of fiber link between master and slave (i).

electrical-electronic-systems-star-interferometer

Figure 4: Star topology for Radio interferometer network with N antennas and different Master to slave delays Equation.

Asymmetric delay error between master and slave decrease slightly increasing fiber link length (Table 2) [13]. The linear approximation of the average is

Equation(13)

µ µ0 (ps), N=10 µ0 (ps), N=100 µ0 (ps), N=1000
10-3 14.11 79.74 98.64
10-4 -7.42 -9.4 -10.23
10-5 1.17 1.15 0.65
10-6 0.10 4.54×10-2 4.32×10-2
10-7 1.112×10-2 1.19×10-2 1.01×10-2
10-8 -7.73×10-4 1.13×10-3 6.97×10-3

Table 2: Offset mean error μe after calibration versus μ and number of slaves N.

Let Equation define asymmetric delay error between Master and slave Equation and meanEquation. Consider random jitter due to repeatability of master to slave delay measurement with 50ps and 30ps (Eq. (14) of standard deviation (Table 2) [13]. Then the global error is the accumulation of jitter error and asymmetric delay error.

Equation(14)

Assuming the linear approximation for the link delay, one gets.

Equation(15)

In order to simulate the overall performance of the synchronization algorithm and its limitations in a distributed radio array, we consider star topology sketched in Figure 4 a cable of length L. Delays and jitters are generated according to Eq. (14)-(15). We set adjustable algorithm parameter Min to 10-12. The number of slaves (N) varies from 10 to 104. Step-size μ may take 10-4, 10-7 or 10-8. Figure 5 illustrate simulation results.

electrical-electronic-systems-synchronization-period

Figure 5: Synchronization period (TSync) vs. number of slaves (N) for different values of algorithm parameter (μ).

Figure 5 shows the synchronization period (TSync) (Figure 6) versus number of slaves (N) for each value of μ. We observe a fast decrease of TSync for increasing N when N ≤ 1000, it stays slightly steady over 2000 slaves for each value of μ [TSync (μ=10-7, N=10) = 2397, TSync (μ=10-7, N=104) =191]. However, it is clear that the synchronization period increase significantly with decreasing μ [TSync (μ=10-7, N=10)=2397, TSync (μ=10-6, N=10)=209].

electrical-electronic-systems-global-mean-error

Figure 6: Global mean error μe (ps) after calibration between master and slaves versus number of iteration (l) for N=100 and μ=10-5.

We consider number of slave N is set to 100, step-size parameter μ set to 10-5. Min is set to 0 (infinity loop in Figure 3). Figure 6 shows global mean error μe (ps) after calibration between master and slaves versus number of iteration (l) (Figure 3). The mean error after calibration decreased linearly versus (l) in the synchronization period TSync. Thereafter the error oscillated around global algorithm accuracy μ0 with peak-to-peak jitter epp (Figure 5). After the simulation analysis the mean error μe it can be presented as fallows at the oscillation zone (Finite error in Figure 6):

Equation(16)

To evaluate the accuracy of the algorithm and compare it with algorithm in reports [13-15], we analyzed an algorithm mean error (Eq. (16)) for each number of slaves (N=10, 100 or 1000) and varying μ. Min is set to 0. Table 2 illustrates the accuracy of the global time synchronization μ0 in picoseconds versus step-size parameter μ. Algorithm maintained sub-ns accuracy for several values of μ and N (Table 2). It is clear that μ0 decreased rapidly with decreasing μ. It changed from 14.11ps for (N=10, μ =10-3) to -7.73 × 10-4 for (N=10, μ =10-8). On the other hand, we can see that the important is N (N ≥ 100), the better accuracy was well when μ ≤ 10-5. We also observed that the accuracy was much better when N=10 and μ ≥ 10-4 compared to others (Table 2).

Quite surprisingly, the synchronization period (TSync) decreased rapidly with increasing number of slaves (Figure 5). This may be induced by the varying length of the error estimation vector (N) (Figure 3). The more bigger N, the better is the mean error estimation. This means that the time synchronization period is minimal in widely distributed arrays.

The proposed algorithm may achieve a prescribed accuracy (Min). It depends on step-size parameter (μ) and number of slaves (N) (Table 2). However, in order to obtain a converging algorithm, Min have to be chosen greater than |μe| (Eq. (16)), because the limiting accuracy of the algorithm is fixed by μe. In the perfect case, Min has to be chosen close to |μe|. Furthermore, from results shown in Figure 5, we can see that the synchronization period increase rapidly with μ. According to these results, we concluded that we may control global algorithm accuracy by adjusting the parameters Min and μ.

The above evaluation shows that global time synchronization can affectively achieved with sub-ns accuracy in distributed networks. The proposed algorithm can compensate offset asymmetric delays with adjustable accuracy bellow 10 ps. (Table 2). The proposed algorithm performed better then [13,16]. Therefore, accuracy may reduce in real hardware implementation [17,18].

Conclusions and Future Work

Overall, in this paper we suggested global time synchronization algorithm in distributed network such as a radio interferometer array with sub-ns accuracy. The main result of this research is an iterative algorithm for asymmetric offset delays error compensation and minimization. We illustrate that the synchronization period and accuracy can be controlled with algorithm parameters. The proposed algorithm can achieved accuracy better than 10ps. Besides, algorithm hardware implementation may be possible and computational complexity is reduced comparing with algorithms developed previously (Table 2).

Master Hardware architecture (Figure 7) for global time synchronization algorithm implementation and testing in radio interferometer networks of 4 slaves is on-going. This board is based on:

i. Programmable delay chips (MC100EP195) for offsets delay adjustment with 10ps accuracy.

ii. Ultra low jitter (100fs) cleaner PLL for clocks generation (LMK03328).

iii. Quad channel time measurement device TDC (THS788) with 8ps accuracy and 13ps jitter

iv. Low skew (8ps) clocks distribution (1:4).

Finally, Virtex-6 FPGA board (ML605) will be used for offset delays computation and adjustment.

electrical-electronic-systems-global-synchronization

Figure 7:Global synchronization Master hardware architecture basing on TDC and DTC devices.

Acknowledgment

The authors would like to thank Exploration Spatiale des Environnements Plantaires (ESEP), for thesis funding.

References

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