A 800 MHz-1.1 GHz 1.2 mW Delay Locked Loop with a Closed Loop Duty Cycle CorrectorBoghrati H and Maranjabi Ali*
School of Electrical and Computer Engineering, Isfahan University of Technology, Iran
- *Corresponding Author:
- Maranjabi Ali
School of Electrical and Computer Engineering
Isfahan University of technology, Iran
Tel: +98 31 1391 3110
E-mail: [email protected]
Received Date: February 19, 2016; Accepted Date: March 21, 2016; Published Date: April 10, 2016
Citation: Boghrati H, Ali M (2016) A 800 MHz-1.1 GHz 1.2 mW Delay Locked Loop with a Closed Loop Duty Cycle Corrector. J Electr Electron Syst 5:179. doi:10.4172/2332-0796.1000179
Copyright: © 2016 Boghrati H, et al. This is an open-access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.
In this paper a low power delay locked loop with a closed loop duty cycle corrector is proposed. The duty cycle corrector circuit is a dual loop circuit which receives a clock signal with 30%~70% duty cycle and generates a clock signal with 50% ± 2% duty cycle. Thepowerconsumption of the overall circuit is 1.2 mW. This circuit is fabricated in 0.18 um CMOS technology. Measurement results show that the RMS jitter of the proposed work is 4 ps at 1 GHz.