alexa A New Fast Access Low Power Multilevel Cache Architect
ISSN ONLINE(2320-9801) PRINT (2320-9798)

International Journal of Innovative Research in Computer and Communication Engineering
Open Access

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Research Article

A New Fast Access Low Power Multilevel Cache Architecture

Janeera.D.A, Dr.H.Mangalam
  1. PG student[Applied Electronics], Department of ECE, Sri Krishna College of Engineering and Technology, Coimbatore, India
  2. HOD, Department of ECE, Sri Krishna College of Engineering and Technology, Coimbatore, India
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Abstract

Cache write-through policy is more efficient and offers better performance in high performance microprocessors compared to write-back policy. Here, write is done synchronously to cache as well as the main memory. The drawback of write-through policy is the large energy overhead due to frequent lower lever cache accesses during write operations. A new cache architecture is proposed here in order to reduce the power consumption and increase the speed of data access. Here, a tag is attached to each way in the L2 cache. This way tag is stored in way-tag array in L1 cache. Utilizing these tags, L2 cache can be accessed as a direct mapping cache during subsequent write hits, thereby power consumption is reduced. A fast counting Bloom Filter is introduced to accurately predict the cache miss. A considerable energy saving is obtained based on SPEC CPU2000 benchmarks along with a small area overhead and no performance degradation. High-performance microprocessors now-a-days use longer addresses and hence cache tag arrays become longer. This architecture can also be applied to other existing cache design techniques to achieve further power reduction and improved delay.

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