alexa A Novel Approach to Reduce Area and Power for FFT Implementation
ISSN ONLINE(2278-8875) PRINT (2320-3765)

International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering
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Special Issue Article

A Novel Approach to Reduce Area and Power for FFT Implementation

Anumol B. Chennattucherry1 and Diego James2
  1. M.Tech Student, Dept. of Electronics and Communication, St. Joseph’s College of Engineering and Technology, Palai, India
  2. Asst. Prof, Dept. of Electronics and Communication, St. Joseph’s College of Engineering and Technology, Palai, India
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Abstract

The Fast Fourier Transform (FFT) is a critical block widely used in digital signal processing algorithm. With the advent of semiconductor processing technology in VLSI system, different approaches had been tried in order to optimize the algorithm for a wide variety of parameters such as area, power and speed. In this paper, we propose to design a FFT block which is capable of computing N point FFT based on Radix-2 Decimation-In-Time (DIT) architecture with carry select adder (CSLA) and a gate level modification to CSLA. Here our goal is to implement Radix-2 N-point FFT in hardware using hardware language (VHDL). Simulation of design units is done in ModelSim- Altera Starter Edition and synthesized using Xilinx ISE 8.1. The overall area and power are reduced

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