Special Issue Article
Area Efficient Digital Comparator Design Using Pseudo NMOS and Pass Transistor Logic
Comparators are one of the most key design elements for a large number of applications. This paper presents wide-range, area efficient and high-speed comparator using pseudo nMOS and pass transistor logic. The conventional CMOS design requires more number of transistors than pseudo nMOS and pass transistor logic. Hence the transistor count of a design can be reduced by using pseudo nMOS and pass transistor logic instead of conventional CMOS. The working operation of the comparator based on a novel scalable parallel prefix structure. The comparison starts from most significant bits (MSB) of each sequence, if the MSB bit of two different sequences is equal that time only the comparison operation moves towards the least significant bit (LSB). This method helps to minimize the dynamic power dissipation by eliminating unwanted transitions in a parallel prefix structure. Then the N-bit comparison result will be generated after [⌈log4N⌉+ ⌈log16N⌉+ 4] CMOS gate delays. This comparator is designed by interconnecting CMOS gates with a maximum number of fan-in and fan-out of five and four, respectively, not depending on comparator bitwidth. This comparator plays a role for high speed and power efficiency for large bitwidth.