Special Issue Article
Bus Functional Model Verification IP Development of AXI Protocol
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The complications of System-on-a-Chip (SoC) functional verification have become more and more complexity. To improving verification productivity and avoiding respins have led to a structured, design-for-verification methodology. In the past decades, many functional verification tools and methodologies have been developed, including simulators, formal verification and debugging tools. Constraints Random Verification (CRV) combines automatic test generation, self-checking test benches, and coverage metrics to significantly reduce the time spent on verifying a design and ensuring throughput of verification by developing Verification Intellectual Property (VIP) for different on-chip interconnect Intellectual Property (IP) blocks on SoCs. The proposed Methodology of Coverage Driven Constraint Random Verification is validated using illustrative example of Advanced microcontroller bus architecture (AMBA) advanced extensible interface (AXI) Protocol for on-chip bus infrastructure where in development design process involves 35% of Designers interference and 65% of Verification Interference. This paper provides a unique approach for successful completion of design and verification with reduced development design cycle.