alexa Delay Locked Loop Using Glitch Free Nand- Based DCDL
ISSN ONLINE(2278-8875) PRINT (2320-3765)

International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering
Open Access

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Research Article

Delay Locked Loop Using Glitch Free Nand- Based DCDL

S.Kokilamani1, K.R.Nimisha2
  1. PG Scholar, Dept. of ECE, Sri Eshwar College of Engineering, Coimbatore, Tamilnadu, India 1
  2. Assistant professor, Dept. of ECE, Sri Eshwar College of Engineering, Coimbatore, Tamilnadu, India 2
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Abstract

A delay locked loop (DLL) is used to synchronize the external and internal clock. This is used to reduce the clock-deskew problem. The main block in DLL is delay line. Digitally controlled delay lines (DCDL) exhibits a glitching problem. This glitching problem is reduced by using NAND-Based DCDL. Sense amplifier based driving circuit is used to control the control bits in DCDL. The proposed DCDL is adopted in the DLL in order to reduce the power and delay time.

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