Design and Implementation of 8-Bit SAR ADC with Built-in-Self- Calibration and Digital-Trim Technique
The successive approximation register (SAR) topology is probably the one that has benefited most from CMOS technology evolution, and is now a strong competitor with other architectures as the pipeline, for medium-resolution medium speed ADCs, and the flash, for low-resolution high-speed ADCs. In this system, propose a SAR ADC with a very low-power background calibration technique that continuously nullifies the comparator offset and operates within the supply-voltage range of the ADC. This method allows the comparator to be implemented with small transistors, reducing the power consumption. Furthermore, being a continuous calibration procedure, it is automatically adapting to changes in process, voltage, and temperature (PVT).For operating with a supply voltage as low mV compare with existing methods, close to the transistors threshold voltage V , the ADC employs local voltage boosting for all the MOS switches. To avoid this TH solution to be a strong penalty to the available area/power budget, a voltage-booster (VB) with minimal complexity is employed.