Design and Implementation of Runtime Reconfigurable High Resolution Digital Pulse Width Modulator on FPGA
|Rajini K. R.1, Shubha G. N.2
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Digitally controlled pulse width modulator have gained increased attention because of a number of potential advantages including lower sensitivity to parameter variations, programmability, reduction or elimination of external passive components, as well as possibilities to implement more advanced control, calibration, or protection algorithms. This paper describes a design and implementation of runtime reconfigurable high-resolution digital pulse width modulator on low-cost general-purpose field-programmable gate arrays (FPGAs) without any manual placement and routing effort. This implementation does not depending on specialized phase locked loop (PLL) or high performance digital clock managers (DCM) which are presents exclusively in high-end vertex-6 FPGA. This implementation based on internal carry chains and logic resources, which are presents in most FPGA families. The proposed DPWM combines a counter based approach with a tapped delay line scheme for increased resolution without unnecessarily increasing the clock frequency. The experimental results show an implementation in a low-cost FPGA (Xilinx Spartan-3) that uses a 1 MHz clock frequency for a final time resolution under 1ps.