alexa Design for Test for MIPS Multi – cycle processor and
ISSN ONLINE(2320-9801) PRINT (2320-9798)

International Journal of Innovative Research in Computer and Communication Engineering
Open Access

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Research Article

Design for Test for MIPS Multi – cycle processor and OpenSPARC T1 Processor

Nikunj Vadodaria and Bhavesh Soni
  1. PG Student, Dept. of VLSI, U. V. Patel College of Engineering, Ahmedabad, India
  2. Asst. Professor, Dept. of Electronics and Communication, U. V. Patel College of Engineering, Kherva, India
Related article at Pubmed, Scholar Google


The purpose of this paper is to understand the process of DFT to be performed on a particular design using the SYNOPSYS tool set. Verification of which can be done at the end by the count of number of DRC’s (Design Rule Check) violations in the process. All the faults should be checked to get the fault free design based on the theoretical background available. The process is then followed on the SYNOPSYS tools for the removal of faults and also for the verification of the same.


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