Design of an Area Efficient Adder Using Minority Gates in QCA
The area and complexity are the major issues in circuit design. As transistors decrease in size more and more of them can be accommodated in a single die, thus increasing chip computational capabilities. However, transistors cannot get much smaller than their current size. The Quantum-dot Cellular Automata (QCA) approach represents one of the possible solutions in overcoming this physical limit. Here a Ripple Carry Adder (RCA) module is proposed that can serve as a basic component for QCA arithmetic circuits. The main methodological design innovation over existing state of the art solutions was the adoption of so called minority gates in addition to the more traditional majority voters. The proposed adder is designed and simulated using QCA designer 2.0.2. Simulation results show that the proposed adder outperforms all state of-the art competitors and reduces area-delay efficiently than previous designs.