Design of Low Cost Image Scaling Processor Using Single Line Buffer Based on VLSI Architecture
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Image scaling is the process of resizing a digital image. It is one of the most important methods used in various applications such as sharpening of an image, image zooming, preserving edge structures in an image and so on. This paper proposes an efficient scaling algorithm for designing an image scaling processor. The proposed scaling algorithm consists of two combined prefilters and one simplified bilinear interpolator. Besides, the replacement of spurious-power suppression technique (SPST) adder of a reconfigurable calculation unit is used to reduce power consumption and filter out the unused switching power. This paper also presents an efficient VLSI architecture for the existing method. The co-operation and hardware sharing techniques greatly decrease the hardware cost requirements. Compared to conventional schemes, the proposed image scaling processor design can reduce the memory requirement and needs only one-line buffer memory.