alexa Design of Multichannel Sample Rate Convertor
ISSN: 2332-0796

Journal of Electrical & Electronic Systems
Open Access

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Research Article

Design of Multichannel Sample Rate Convertor

Jain V* and Agrawal N

Department of Electronics and Communication, College of Technology and Engineering, MPUAT, Udaipur, India

*Corresponding Author:
Jain V
Department of Electronics and Communication
College of Technology and Engineering MPUAT
Udaipur, India
Tel: 0294-247-1302
E-mail: [email protected]

Received Date: November 12, 2015; Accepted Date: December 29, 2015; Published Date: January 01, 2016

Citation: Jain V, Agrawal N (2016) Design of Multichannel Sample Rate Convertor. J Electr Electron Syst 5:168. doi:10.4172/2332-0796.1000168

Copyright: © 2016 Jain V, et al. This is an open-access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.

 

Abstract

The multiobjective design of multichannel sample rate convertor using Genetic optimization technique is considered in this paper. This new optimization tool is based on mechanism of biological evolution. It is characterized by design of natural system retaining its robustness and adaption properties of natural systems. The objectives of multichannel sample rate convertor design include matching some desired response while having minimum linear phase; hence, reducing the time response, constant group delay, increasing bandwidth. Genetic optimization technique is also used for reducing the power consumption of multichannel sample rate convertor by optimization of coefficient of filter by scaling which are used in implementation of multichannel sample rate convertor design in FPGA implementation. After applying genetic algorithm 1 to 128 channel sample rate convertor bandwidth increased by 150%, power reduced by 62% to 85%, dynamic power reduced by 31% to 54% of conventional sample rate convertor, constant and less group delay, linear phase response, reducing time response. In an extended work the authors have tried and successfully executed the model and system upto 128 channels. The proposed model is first designed on simulink platform using Xilinx Blockset and then it is transferred on FPGA platform using system generator. The complete circuit is synthesized, implemented, simulated using Xilinx design suite.

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