Design of Wishbone Point to Point Architecture and Comparison with Shared Bus
System on chip is integration of multimillion transistors in single chip for reducing the cost of design. With the new level of integration the System on Chip design is methodology where intellectual property blocks combined on single chip and allow huge chips to be design at acceptable cost and quality. Hence a standard interface bus protocol is required to increase the productivity with design time reduction. Wishbone is flexible System on Chip bus architecture, connecting IP cores together and alleviating System on Chip integration problems. Wishbone can communicate over variety of devices. Motivated by this, this paper presents different feature of wishbone bus interface. TheSoC design with DMA master cores and memory slave cores using wishbone point to point interconnection and shared bus interconnection scheme has been designed in Xilinx 12.3. This paper investigates and compare wishbone interconnection point to point and shared scheme.