Efficient Implementation of Fault Coverage Circuit for High Speed and Low Power Applications
|A.S.R.N.Raju1, C .Malleswar2
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Test Pattern generation has long been carried out by using Linear Feedback Shift Registers (LFSR’s). LFSR’s are a series of flip-flop’s connected in series with feedback taps defined by the generator polynomial. The seed value is loaded into the outputs of the flip-flops. The only input required to generate a random sequence is an external clock where each clock pulse can produce a unique pattern at the output of the flip-flops. This random sequence at the output of the flip-flops can be used as a test pattern. The number of inputs required by the circuit under test must match with the number of flip-flop outputs of the LFSR. To reduce the power by maintaining the fault coverage in these project three intermediate patterns between the random patterns is generated. The goal of having intermediate patterns is to reduce the transitional activities of Primary Inputs (PI) which eventually reduces the switching activities inside the Circuit under Test (CUT) and hence power consumption is also reduced without any penalty in the hardware resources. The experimental results for c17 benchmark, with and without fault confirm the fault coverage of the circuit being tested. In the paper the power is mention that 14mw. Now the proposed system has to reduce it to less than 14mw i.e. nearly 12mw. At the same time we will reduce the device utilization also.