Special Issue Article
FPGA Design of Reconfigurable Binary Processor Using VLSI
Binary image processing is a powerful tool in many image and video applications. In this paper we proposed efficient hardware architecture of Binary image processor for low power applications and also propose an Efficient Majority Logic Fault Detection algorithm on binary image processor to reduce the error rate. Binary image processor’s architecture is a combination of input and output control units, reconfigurable binary processing module, processor control unit, register group and bus interfaces. The reconfigurable binary processing module consists of mixed-grained reconfigurable binary compute units and output control logic and it also performs mathematical morphology operations. The simulation and experimental results demonstrate that the processor is suitable for real-time binary image processing applications. The proposed binary processor is designed using Verilog HDL, simulated using Modalism software and synthesized using Xilinx project navigator.