FPGA Implementation of Optimized Decimation Filter for Wireless Communication Receivers
Digital down converter (DDC) is very important and integral part of the multi-rate wireless communication system. As it utilizes the major resources, therefore its low cost and efficient implementation is of main concern. This paper presents and implements a FPGA based optimized design of decimation filter for wireless communication receivers. Cascaded integrated comb (CIC) filters are multiplier less linear filters which are extensively used in multi-rate systems for the purpose of digital down conversion (DDC). An optimized architecture based upon these filters is analyzed and implemented. The prototype of the proposed filter is designed to decimate the input signal having sampling rate 10 MHz, by the decimation factor of 8 using Matlab-Simulink Model and Xilinx System Generator. The design is implemented on Vertex-5 based xc5vlx110t-3-ff1136 target device. The proposed design consumed considerably less resources on the target device to provide an efficient design for multi-rate wireless communication receivers.