Glitch Free Strobe Control Based Digitally Controlled Delay Lines
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The Combinational circuit designed was glitch free NAND-based digitally controlled delay-lines (DCDL) present a glitching problem which may limit their employ in many applications. The glitch free strobe-control based digitally controlled delay lines overcame this limitation by opening the employ of glitch free NAND-based DCDLs in a wide range of applications. The proposed glitch free strobe-control based digitally controlled delay lines maintains the same resolution and minimum delay of previously proposed glitch free NAND-based DCDL. Following this analysis, three driving circuits for the delay control-bits are also proposed. Proposed DCDLs have been designed in a 90-nm CMOS technology. Simulation results show that new circuits result in the lowest resolution, with a little worsening of the minimum delay with respect to the previously proposed DCDL with the lowest delay. Simulations also confirm the correctness of developed glitching model and sizing strategy. As example application, proposed DCDL is used to recognize an Alldigital spread-spectrum clock generator (SSCG). The use of proposed DCDL in this circuit allows to reduce the peak-to-peak absolute output jitter with respect to a SSCG using three-state inverter based DCDLs.