Special Issue Article
High Speed Boosted CMOS Differential Logic for Ripple Carry Adders
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This paper describes a high speed boosted CMOS differential logic which is applicable in Ripple Carry Adders. The proposed logic operating with supply voltage approaching the MOS threshold voltage. The logic style improves switching speed by boosting the gate-source voltage of transistors along timing critical signal path. It allows a single boosting circuit to be shared by complementary outputs as a result the area overhead also minimizes. As compared to the conventional logic gates the EDP (energy delay product) is improved. The test sets of logic gates and 64 bit adders where designed in tsmc0.18μm CMOS process. The experimental result for 64bit Ripple Carry Adders using the proposed logic style revealed that the addition time is reduced as compared with the conventional CMOS circuits.