IMPLEMENTATING PROTECTED AND LESS COMPLEX CRIPTO DEVICES WITH HIGH FAULT EXPOSURE
The main motive of this Thesis is to design a secured crypto device with less complication and high protection by means of “ADVANCED AES” Algorithm along with self test procedure. The discriminating application of technological and associated procedural safeguards is an significant liability of every Federal organization in providing sufficient security to its electronic data systems and coming to self test concept there are two main functions that must be performed on-chip in order to implement built-in self-test (BIST): test pattern generation and output response analysis. The most common BIST schemes are based on pseudorandom test pattern generation using linear feedback shift registers (LFSR’S) and output response compaction using signature analyzers. To accomplish high security for a system we are using the crypto devices technique.