Implementation of Adaptive Viterbi Decoder on FPGA for Wireless Communication
|Parameshwara R 1, Ganesh V.N 2
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A new trend in wireless communication systems has dictated the need for dynamical adaptation of communication systems in order to suit environmental requirements. Wireless networks usually employ sophisticated Forward Error Correction (FEC) techniques such as Viterbi Algorithm to combat with the channel distortion effects such as multipath fading and intersymbol interference. Viterbi algorithm is employed in wireless communication to decode the Convolution codes; these are the class of FEC codes. Such decoders are complex & dissipates large amount of power. Thus this paper presents the design of an Adaptive Viterbi Decoder (AVD) that uses survivor path with parameters in an attempt to reduce the power and cost and at the same time increase in speed. Most of the researches aimed to reduce power consumption or work with high frequency for using the decoder in the modern applications such as 3 GPP, DVB, and wireless technology. Field Programmable Gate Array technology (FPGA) is considered as highly configurable option for implementing many sophisticated signal processing tasks. The proposed viterbi decoder design is simulated on Modelsim.SE6.3f and implemented using VHDL code.