alexa Implementation of LMS-ALE Filter using Vedic Algorithm | OMICS International | Abstract
ISSN: 2168-9679

Journal of Applied & Computational Mathematics
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Short Communication

Implementation of LMS-ALE Filter using Vedic Algorithm

Jintu K Joseph1* and Purushotham U2

1Department of VLSI and Embedded systems, Visvesvaraya Technological University, PESIT, Bangalore, India

2Department of Electronics and Communications, Visvesvaraya Technological University, PESIT, Bangalore, India

*Corresponding Author:
Joseph JK
VLSI and Embedded systems, Visvesvaraya Technological University
PESIT, Bangalore, India
Tel: 0831-2498100
E-mail: [email protected]

Received July 17, 2015; Accepted July 25, 2015; Published July 30, 2015

Citation: Joseph JK, Purushotham U (2015) Implementation of LMS-ALE Filter using Vedic Algorithm. J Appl Computat Math 4: 237. doi:10.4172/2168-9679.1000237

Copyright: © 2015 Joseph JK, et al. This is an open-access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.

Abstract

ALE or adaptive line Enhancers are special kinds of adaptive filters widely used in noise cancellation circuits. In circuits where we don’t have any prior knowledge of signal and noise, fixed filters unit never works good. Among adaptive filter ring algorithms LMS algorithm is very common, in our work also we use LMS algorithm. LMS-ALE filters removes the sinusoidal noise signals present in the channel by calculating the filter coefficients in every iteration. LMS-ALE filter has large number of multiplier units. FFT or Fast Fourier Transform blocks present in LMS algorithm again consist of large array of multiplier units. Optimization of LMS-ALE filter lies must start from optimization of multiplier blocks. Here we use Vedic “Vertical and crosswise algorithm” for multiplier design. When compared to conventional booth multiplier based LMS-ALE filter units, Vedic multipliers gives more performance in areas like resource utilization, power requirement, delay etc. The work includes designing Vedic multipliers, complex Vedic
multipliers, redesigning Radix-8 FFT using Vedic multipliers, redesigning LMS block using Vedic FFT, redesigning LMS ALE filter using Vedic multipliers and Vedic LMS blocks. Major part of design is done in Verilog using Xilinx ISE design suite. ADC block present in LMS-ALE filter is done in Matlab version 2013.

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