Low Power Pass Transistor Logic Flip Flop
In this brief, a low-power flip-flop (FF) design PTLFF: Pass Transistor Logic Flip Flop is presented. The pro-posed design successfully adopts two measures to overcome the problems associated with existing P-FF designs. The first one is reducing the number of nMOS transistors stacked in the discharging path. The second one is supporting a mechanism to conditionally enhance the pull down strength when input data is “1.” long discharging path problem in conventional explicit type pulse-triggered FF (P-FF) designs and achieves better speed and power performance. Based on post-layout simulation results using TSMC CMOS 90-nm technology, the proposed design outperforms the conventional P-FF design by using only 17 transistors. The average power delay is reduced to 3.57 μW.