Mitigating the Impact of NBTI and PBTI Degradation
Bairy B, Craig TS, Eshaghian-Wilner MM*, Gonde K, Gupta N, Prajogi A and Saligram R
Department of Electrical Engineering-Systems, University of Southern California, USA
- Corresponding Author:
- Mary Mehrnoosh Eshaghian-Wilner
University of Southern California, USA
E-mail: [email protected]
Received date: March 24, 2016; Accepted date: April 19, 2016; Published date: May 24, 2019
Citation: Bhuvana B, Thomas Soren C, Mary EW, Kalyani G, Naman G, et al.
(2016) Mitigating the Impact of NBTI and PBTI Degradation. Global J Technol
Optim 7:195. doi:10.4172/2229-8711.1000195
Copyright: © 2016 Bairy B, et al. This is an open-access article distributed under
the terms of the Creative Commons Attribution License, which permits unrestricted
use, distribution, and reproduction in any medium, provided the original author and
source are credited.
Modern CMOS devices encounter a major problem that alters the threshold voltages of the NMOS and PMOS. Negative Bias Temperature Instability (NBTI) and Positive Bias Temperature Instability (PBTI) are common ageing phenomena observed in PMOS and NMOS devices, respectively. Due to operating temperature and stress time, NBTI and PBTI create a decrease in drain-to-source current and an increase in propagation delay. Threshold voltage is an important parameter due to exponential dependence on delay and leakage power. Threshold voltage variations produce adverse effects on operation frequency. These phenomena accrue in pull-up/pull-down transistors in stack and vastly degrade CMOS performance. This paper discusses the various factors responsible for NBTI and PBTI and the challenges associated with modeling these effects due to the recovery mechanism exhibited by the transistors when the stress is removed. Therefore, we propose an algorithm to reduce the effects of NBTI and PBTI that will reduce the stress time for each transistor through the relative repositioning of the transistors based on the signal probability.