Journal of Electrical & Electronic Systems

Analysis of Power Reduction Techniques used in Testing of VLSI Circuits

Abstract

Shaktisinh Karnubha Jadeja, Rajendra Pate and Jayesh Popat

One of the most important parameter over the past decade in VLSI design is the Power dissipation during manufacturing test, as the circuit consume much more power during test than functional mode of operation. This paper presents analysis of low power testing techniques by which Power optimized test patterns are obtained. The compaction technique has been validated using benchmark examples, and it has been shown that average 33% of test patterns have been reduced by which power is minimized. Evaluation of various techniques under consideration in this paper is carried out by open source tool ATALANTA for test pattern generation and MATLAB for optimization.