Photonic Approach to Optimize Energy Consumption for On-chip Clos Network
- *Corresponding Author:
- Deepalakshmi B
Department of Applied Electronics
Arunai Engineering College
Tel: 04175 255 102
E-mail: [email protected]
Received date: April 29, 2015; Accepted date: February 23, 2016; Published date: March 01, 2016
Citation: Deepalakshmi B, Maruthachalam G (2016) Photonic Approach to Optimize Energy Consumption for On-chip Clos Network. J Laser Opt Photonics 3: 128. doi:10.4172/2469-410X.1000128
Copyright: © 2016 Deepalakshmi B, et al. This is an open-access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.
To meet energy-efficient performance needs, the computation has positioned to parallel computer architectures, such as chip multiprocessors (CMPs), internally interconnected via networks-on-Chip (NoC) to achieve increasing communication needs. To accomplish scaling execution as center include increment to the hundreds future CMPs, all things considered, will require elite, yet vitality productive interconnects. Silicon Nano photonics is a promising swap for electronic on-chip interconnect for its high data transfer capacity and low inactivity, by the by, earlier methods have required high static force for the laser and warm ring tuning. We propose novel Nano photonic NoC (PNoC) design, upgraded for elite and force effectiveness. This paper makes three essential elements: a novel, Nano photonic engineering which isolates the system into subnets for better productivity; an exclusively photonic, inband, appropriated discretion plan; and a channel sharing schematic are using the same waveguides and wavelengths for intervention as information transmission. As a result the interconnection can be reduced latency with increased throughput.