alexa Power Circuit Topology for the reduction in size of DVR
ISSN ONLINE(2278-8875) PRINT (2320-3765)

International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering
Open Access

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Research Article

Power Circuit Topology for the reduction in size of DVR

Joffie Jacob1, Reshmi V2
  1. PG Scholar, Department of Electrical Engineering, Amal Jyothi College, Kerala, India
  2. Assistant Professor, Department of Electrical Engineering, Amal Jyothi College, Kerala, India
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Abstract

With the increased use of sophisticated electronic equipments, high efficiency variable speed drives and power electronic controllers power quality has become a rising concern to both utilities and customers. Voltage sag is the most common power quality problem generally caused by faults in transmission/distribution sector. Voltage sag even lasting only for a few tens of milliseconds is enough to bring entire production lines to standstill causing considerable economic loss. Therefore necessary measures have to be taken to protect sensitive loads which are susceptible to these voltage disturbances. Among the available solutions, Dynamic Voltage Restorer (DVR) is a series connected cost effective custom power device that can quickly mitigate the voltage sag in the system and restore the load voltage to the pre-fault value. Traditional DVR consists of series and shunt converters connected back-to-back and a dc capacitor installed on the common dc link. But the cost, weight, and physical size have inhibited the DVR from greater penetration and wider recognition. In this paper, two no energy (source side and load side connected shunt converter) system topologies for dynamic voltage restorers are analysed based on the storage element required for sag mitigation. In the former case the dc capacitor is required to store the necessary energy for compensation but in the latter case it is required only for smoothing the dc-link voltage so that size of the energy storage element required can be reduced significantly. A synchronous reference frame based controller for the inverter based voltage sag compensator is presented. This paper also deals with a method to mitigate the zero-sequence voltage component in the load after the occurrence of an unbalance voltage sag. Simulations are carried out in PSCAD software package.

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