alexa Review on Distributed Canny Edge Detector using FPGA
ISSN ONLINE(2278-8875) PRINT (2320-3765)

International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering
Open Access

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Review Article

Review on Distributed Canny Edge Detector using FPGA

Poonam S. Deokar, Amruta R. Kaushik, Kirti B. Satale
Assistant professor, Department of E&TC, KVNNIEER, Nashik, Maharashtra, India
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Abstract

Edges are boundaries between different textures. Edge also can be defined as discontinuities in image intensity from one pixel to another. Modem image processing applications demonstrate an increasing demand for computational power and memories space. Typically, edge detection algorithms are implemented using software. With advances in Very Large Scale Integration (VLSI) technology, their hardware implementation has become an attractive alternative, especially for real-time applications. The Canny algorithm computes the higher and lower thresholds for edge detection based on the entire image statistics, which prevents the processing of blocks independent of each other. The Canny edge detector has remained a standard for many years and has best performance. Direct implementation of the canny algorithm has high latency and cannot be employed in real-time applications. To overcome these, an adaptive threshold selection algorithm is proposed, which computes the high and low threshold for each block based on the type of block and the local distribution of pixel gradients in the block. Distributed Canny Edge Detection using FPGA reduces the latency significantly; also this allows the block-based canny edge detector to be pipelined very easily with existing block-based codec.

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