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ISSN: 2168-9695

Advances in Robotics & Automation
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Review Article

Synthesis of Custom Hardware from ADA with Artificial Intelligence Techniques

Michael Dossis*

Department of Informatics Engineering, TEI of Western Macedonia, Kastoria Campus, Fourka Area, Kastoria, GR 52 100, Greece

*Corresponding Author:
Michael Dossis
Department of Informatics Engineering
TEI of Western Macedonia, Kastoria Campus
Fourka Area, Kastoria, GR 52 100, Greece
Tel: 30-694-6154078
E-mail: [email protected]

Received May 27, 2014; Accepted June 05, 2014; Published June 07, 2014

Citation: Dossis M (2014) Synthesis of Custom Hardware from ADA with Artificial Intelligence Techniques. Adv Robot Autom 3:121. doi:10.4172/2168-9695.1000121

Copyright: © 2014 Dossis M. This is an open-access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.


The advancing complexity of contemporary microelectronics has motivated research in high-level and system synthesis (HLS). Formal and intelligent HLS techniques are presented in this contribution, thus the generated implementation is correct-by-construction. These intelligent techniques include RDF (Resource Description Framework) and logic relations, along with automatic implementation options and they are employed for the transformations of a hardware compiler. The proposed toolset utilizes compiler-generators, RDF rules and logic programming in combination with XML validation of the internal state of the compiler. These intelligent and formal techniques make the whole transformation from source code to implementation, formal. The HLS tool is enhanced with the Parallel, Abstract Resource – Constrained Scheduler, which aggressively optimizes the initial state schedules, into maximally parallelized ones. A number of custom options are applied by the user of this toolset, in order to automatically compile selected testcases from real-world applications which prove the usability of the embedded scheduler and the formal compilation of the intelligent HLS compiler.


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