Toward EHW 2.0 - Some Ideas in HDL-Based Evolution of Digital Circuits
Department of Electronics and Telecommunications – “Dunarea de Jos” University in Galati, Romania
- Corresponding Author:
- Rustem Popa
Department of Electronics and
Telecommunications – “Dunarea de Jos”
University in Galati, Stiintei Str., nr. 2
800210, Galati, Romania
Tel: (0236) 460182
E-mail: [email protected]
Received date: January 06, 2015; Accepted date: January 07, 2015; Published date: January 17, 2015
Citation: Rustem P (2015) Toward EHW 2.0 – Some Ideas in HDL-Based Evolution of Digital Circuits. Glob J Tech Opt 6:174. doi: 2229-8711.1000174
Copyright: © 2015 Rustem Popa. This is an open-access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.
Evolvable Hardware (EHW) is a field of Evolutionary Computation (EC) started in the early 1990’s that includes a subfield of Evolvable Hardware Design and a subfield of Adaptive Hardware. Two methods of evolvable hardware design of a one-bit full adder are analyzed in this paper: first method is based on the well-known idea of gate-level design using a network of programmable gates, and the second method uses Verilog instructions coded in chromosomes represented as binary strings. Eventually, the two solutions were compared in terms of hardware resources and propagation times.