Variation Tolerant Clock Distribution Network for NoMicroprocessor
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Clock mesh network is the repeated structure. Therefore network withstand any variations. The variations create clock skew in the circuit. But the skew is minimized in the clock mesh significantly because variation tolerant. The clock mesh networks mostly used in the high end products like microprocessors. Because mesh networks needs high resources compared to clock trees. The network needs more wire lengths and takes more area. In this paper, we present and construct initial mesh structure. The wire length and area minimized in the mesh structure. We try to implement clock mesh in the low end products like ASIC chips.