alexa A 1.35V 4.3GB s 1Gb LPDDR2 DRAM with controllable repeater and on-the-fly power-cut scheme for low-power and high-speed mobile application


Journal of Electrical & Electronic Systems

Author(s): Bong Hwa Jeong, Jongwon Lee, Yin Jae Lee, Tae Jin Kang, Joo Hyeon Lee, Duck Hwa Hong, Jae Hoon Kim, Eun Ryeong Lee, Min Chang Kim, Kyung Ha Lee, Sang Il Park, Jong Ho Son, Sang Kwon Lee, Seong Nyuh Yoo, Sung Mook Kim, Tae Woo Kwon, Jin Hong Ahn, Yong Tak Kim

Abstract Share this page

With the advent of high-performance multi-processing demands for real-time multimedia and broadband networking in battery-based mobile systems, high-speed and low power mobile SDRAM/DDRs are becoming increasingly important. We present an on-the-fly power-cut scheme that can be applied to mobile DRAM without any special modes and a global data-line repeater scheme to reduce the data-line delay. In addition, 4b data prefetch and a ZQ calibrated output driver scheme are used to achieve 4.3 GB/s/chip (1066 Mb/s/pin) bandwidth with 110 mW power dissipation.

This article was published in IEEE International on Solid-State Circuits Conference - Digest of Technical Papers. and referenced in Journal of Electrical & Electronic Systems

Relevant Expert PPTs

Relevant Speaker PPTs

Recommended Conferences

Relevant Topics

Peer Reviewed Journals
Make the best use of Scientific Research and information from our 700 + peer reviewed, Open Access Journals
International Conferences 2017-18
Meet Inspiring Speakers and Experts at our 3000+ Global Annual Meetings

Contact Us

© 2008-2017 OMICS International - Open Access Publisher. Best viewed in Mozilla Firefox | Google Chrome | Above IE 7.0 version