alexa A duty cycle corrector based frequency multiplier


Journal of Electrical & Electronic Systems

Author(s): Mir Mohammad Navidi, Adib Abrishamifar

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In this paper a modified frequency multiplier based on a low power duty cycle corrector is presented. The proposed circuit multiplies the output frequency of a PLL, by 3. Also, the output duty cycle of the multiplier could be controlled by changing the ratio of charging/discharging current of the charge pump. This circuit is simulated by using 0.18 um CMOS process. When the VCO operates at 846MHz the power dissipation of the circuit is 1.16mW at 1.8V supply voltage.

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This article was published in Electrical Engineering (ICEE and referenced in Journal of Electrical & Electronic Systems

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