alexa A fast lock time pulsewidth control loop using second order passive loop filters


Journal of Electrical & Electronic Systems

Author(s): M M Navidi, A Abrishamifar

Abstract Share this page

This paper presents a usage of the second order loop filters for PWCLs. The analysis shows that by using this kind of loop filters, lock time is much better than conventional PWCLs and is comparable with PWCLs using fast locking circuits. Also, power consumption of the PWCLs using second order filters are less than the fast locking PWCLs. A 0 18 um CMOS technology and 1.8 V supply voltage are used to verify the operation of the proposed circuit. The simulation results show that the proposed PWCL reduces the lock time to 405ns. The proposed PWCL operates from 400MHz to 1.4GHz. The duty cycle of the input clock is from 10% to 80% and the duty cycle of the output clock is from 30% to 60% in step of 10%. With an input clock operating at 1GHz lock time and power dissipation of the PWCL are 390ns and 0.187mW, respectively.

  • To read the full article Visit
  • Open Access
This article was published in 19th Iranian Conference on Electrical Engineering (ICEE) and referenced in Journal of Electrical & Electronic Systems

Relevant Expert PPTs

Relevant Speaker PPTs

Recommended Conferences

Relevant Topics

Peer Reviewed Journals
Make the best use of Scientific Research and information from our 700 + peer reviewed, Open Access Journals
International Conferences 2017-18
Meet Inspiring Speakers and Experts at our 3000+ Global Annual Meetings

Contact Us

© 2008-2017 OMICS International - Open Access Publisher. Best viewed in Mozilla Firefox | Google Chrome | Above IE 7.0 version