Author(s): M M Navidi, A Abrishamifar
This paper presents a usage of the second order loop filters for PWCLs. The analysis shows that by using this kind of loop filters, lock time is much better than conventional PWCLs and is comparable with PWCLs using fast locking circuits. Also, power consumption of the PWCLs using second order filters are less than the fast locking PWCLs. A 0 18 um CMOS technology and 1.8 V supply voltage are used to verify the operation of the proposed circuit. The simulation results show that the proposed PWCL reduces the lock time to 405ns. The proposed PWCL operates from 400MHz to 1.4GHz. The duty cycle of the input clock is from 10% to 80% and the duty cycle of the output clock is from 30% to 60% in step of 10%. With an input clock operating at 1GHz lock time and power dissipation of the PWCL are 390ns and 0.187mW, respectively.