alexa A Fast-Locking, Low-Jitter Pulsewidth Control Loop for High-Speed ADC


Journal of Electrical & Electronic Systems

Author(s): Zhangming Zhu, Maliang Liu, Jingyu Wang, Yintang Yang

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A fast-locking, high-precision, and low-jitter pulsewidth control loop (PWCL) for high-speed high-resolution analog-to-digital converter is presented. Only through controlling the delay of rising edge to adjust duty cycle, the clock jitter could be suppressed greatly. An improved charge pump with a follower circuit and self-biased loop was designed to decrease the voltage ripples for higher accuracy and lower jitter. A startup circuit was adopted to enable the pulsewidth control loop lock rapidly. With the SMIC 0.18 μm 3.3 V CMOS process, the simulation and measured results show that within 180 ns the PWCL can lock the clock duty cycles for the accuracy of 50±1% with 10%~90% input duty cycle from 50 to 550 MHz. The rms-jitter is 73 fs at 250 MHz. The active area is about 0.023 mm².

This article was published in IEEE Transactions on Very Large Scale Integration (VLSI) Systems and referenced in Journal of Electrical & Electronic Systems

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