alexa A Low Logic Depth Complex Multiplier Using Distributed Arithmetic.


Research & Reviews: Journal of Engineering and Technology

Author(s): Anders Berkeman

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A combinatorial complex multiplier has been designed for use in a pipelined fast Fourier transform processor. The performance in terms of throughput of the processor is limited by the multiplication. Therefore, the multiplier is optimized to make the input-to-output delay as short as possible. A new architecture based on distributed arithmetic, Wallace-trees, and carry-lookahead adders has been developed. The multiplier has been fabricated using standard cells in a 0.5- m process and verified for functionality, speed, and power consumption. Running at 40 MHz, a multiplier with input wordlengths of 16+16 times 10+10 bits consumes 54% less power compared to an distributed arithmetic array multiplier fabricated under equal conditions.

This article was published in IEEE Journal of Solid-State Circuits and referenced in Research & Reviews: Journal of Engineering and Technology

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