alexa An all-digital 90-degree phase-shift DLL with loop-embedded DCC for 1.6Gbps DDR interface


Journal of Electrical & Electronic Systems

Author(s): JunHyun Bae, JinHo Seo, HwanSeok Yeo, HongJune Park

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An all-digital 90deg phase-shift DLL is proposed for 1.6 Gbps DDR interface by using a loop-embedded DCC and a binary phase detector with the lock range extended to 0~4pi radians. The DCC has a small delay and the fixed rising-edge property for loop-embedding. The chip fabricated with a 0.13 um CMOS process gives the DLL data rate of 667 Mbps~1.6 Gbps and the output duty cycle of 47.8%~49% for the input duty cycle of 23%~76%, at 1.6 Gbps and 1.2 V.

This article was published in Custom Integrated Circuits Conference and referenced in Journal of Electrical & Electronic Systems

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