Author(s): PW Hollis, JJ Paulos
A neural network implementation that uses MOSFET analog multipliers to construct weighted sums is described. The scheme permits asynchronous analog operation of Hopfield-style networks with fully programmable digital weights. This approach avoids the use of components that waste chip area of require special processing. Two small chips have been fabricated and tested-one implementing a fully connected (recursive) network and the other containing isolated portions of a neuron. The fully connected network chip successfully solves simple graph partitioning problems, in confirmation of network simulations performed using an analytic model of the analog neuron. This result verifies the operation of the complete network, including common-mode biasing circuits and connection weight data paths. A direct scaling of this chip would allow the complete integration of 81-neuron fully connected networks with 6-b plus sign connection weights using 1.25- mu m design rules on a 1-cm die.