alexa Digital delay locked loop with open-loop digital duty cycle corrector for 1.2Gb s pin double data rate SDRAM


Journal of Electrical & Electronic Systems

Author(s): Chunseok Jeong, Changsik Yoo, JaeJin Lee, Joongsik Kih

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A digital delay locked loop (DLL) for 1.2 Gb/s/pin double data rate (DDR) SDRAM is described, which incorporates duty cycle correction (DCC). The DCC locking information is also stored as a digital code for fast wake-up from power-down mode and DCC control is done in an open-loop, enabling fast locking of the DCC loop with minimum additional power consumption. The DLL, implemented in a 0.35 /spl mu/m CMOS technology, provides an output clock with 64 ps peak-to-peak jitter and the accuracy of the DCC is /spl plusmn/0.7% for /spl plusmn/10% input duty error from 250 MHz to 600 MHz clock frequency. The digital DLL, excluding I/O buffers, dissipates 10 mW from a 2.5 V power supply.

This article was published in Proceeding of the 30th European on Solid-State Circuits Conference and referenced in Journal of Electrical & Electronic Systems

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