alexa Radix-2 FFT butterfly processor using distributed arithmetic.


Research & Reviews: Journal of Engineering and Technology

Author(s): IR MacTaggart, MA Jack

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A parallel-data VLSI architecture for computation of the fast Fourier transform (FFT) is described. The processor is based on a computationally efficient vector rotate algorithm. Use of a 2-dimensional pipeline configuration allows a radix-2 butterfly operation to be performed once every system clock cycle (250 ns) to generate real or imaginary transform components. The architecture is considered to be a computationally efficient VLSI approach for high-bandwidth computation of the FFT. The design and performance of an 8-bit FFT butterfly processor are described.

This article was published in IEEE and referenced in Research & Reviews: Journal of Engineering and Technology

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