700 Journals and 15,000,000 Readers Each Journal is getting 25,000+ ReadersThis Readership is 10 times more when compared to other Subscription Journals (Source: Google Analytics)
Full adder and NAND are the most important parts of digital circuits. Therefore, optimizing the these blocks improves the whole output parameters of digital circuits. In this paper controversial full adder and NAND are designed in CNFET technology and then different parameters of CNFET technology are changed to optimize the speed and power consumption of full adder and NAND. The results of simulation by using HSPICE in .9v are presented. The result of simulation shows the best parameters for better performance of these full adder and NAND in CNFET technology.
Controversial full adder, CNFET, Power consumption, NAND, Chirality vector, #