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Special Issue Article Open Access
This paper presents an algorithm for reducing the hardware complexity of linear phase FIR digital filters. Traditional parallel filter implementations cause linear increase in the hardware cost with respect to the block size. Recently, an efficient parallel FIR filter implementation technique requiring a less-than linear increase in the hardware cost was proposed. This paper makes two contributions. First,the new structure is based on fast FIR algorithm (FFA) that utilizes the symmetry of coefficients; thereby reducing half the number of multipliers in the sub filter section at the expense of increase in adders. Modified FIR filter design using distributed Arithmetic (DA) also provides an approach for multiplier-less implementation of DSP systems. It can completely replace all multiplications and additions by a look up table (LUT) and a shifter-accumulator thereby it can save considerable amount of hardware resources.