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Abu Asaduzzaman

Abu Asaduzzaman

Wichita State University, USA

Title: Microelectronic sensor for DNA analysis

Biography

Abu Asaduzzaman is experienced in collaborative projects that involve research-oriented universities and leading high-tech industries in the U.S.A. Over 10 years of demonstrated teaching excellence in university education in the areas of computer architecture, parallel programing, embedded systems, and performance and power evaluation. Highly skilled in information technology (IT) with over a decade of experience in working with and working for major IT corporate clients (such as Blue Cross and Blue Shield of Florida and ECI IP Incorporated) using cutting edge technology. Extraordinary knowledge and experience of successfully applying innovative techniques for diverse populations of learners into classroom and online teaching. Principle investigator (PI) of many grants including WSU URCP Award 2014-2015, Wiktronics-WSU Embedded Systems Project 2014, Kansas NSF EPSCoR First Award 2013-2014, NVIDIA-WSU CUDA Teaching Project 2013, and M2SYS-WSU Biometrics Project 2012. Reviewed many NSF programs including TUES, GRFP, and EPSCoR RSV Panel-2. Authored more than 80 peer-reviewed research articles. TPC/IPC member of various conferences including IEEE IPCCC/ICCIT. Member of IEEE, ASEE, PKP, TBP, etc.

Abstract

Multicore architectures suffer from high core-to-core communication latency due to the traditional wire based network and power-hungry cache’s unpredictable behavior. As the number of cores increases, managing the requests from many cores and satisfying the large number of requests as quickly as possible becomes a critical challenge. Studies suggest that a directory with the information about Level-1 Cache (CL1) blocks can be helpful in order to reduce the communication latency. The recently introduced wireless router in network-on-a-chip shows promise by efficiently handling many requests, simultaneously, faster and cheaper (consuming less energy). Therefore, we introduce a Level-2 Cache Mediator (L2CM) and a hybrid network (with wired and wireless routers) into a multicore/many-core system to improve system scalability. The proposed L2CM should have enough memory to store information about CL1 cached blocks, CL1 victim blocks, etc., and a wireless router for low-power fast communication with Central Processing Unit (CPU) cores. According to the experimental results, (considering communication delay and power consumption) the proposed architecture is better than mesh multicasting for all cases and is better than or as good as wireless network-on-a-chip. Experimental results suggest that the proposed L2CM may decrease the communication delay by up to 63% and the total power consumption by up to 33%.