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Hassan Mostafa

Hassan Mostafa

Cairo University, Egypt

Title: Next Generation FPGA: Challenges and Opportunities

Biography

Dr. Hassan Mostafa (S’01, M'11, SM'15) received the B.Sc. and M.A.Sc degrees from Cairo University, Egypt, in 2001 and 2005, respectively, and the P.h.D. degree from University of Waterloo, Canada in 2011. He is currently an Assistant Professor at the Electronics and Communications Department, Cairo University, Cairo, Egypt and also an Adjunct Assistant Professor at the Center for Nano-electronics and Devices (CND) at the American University in Cairo (AUC), Cairo, Egypt. Dr. Mostafa has worked as an NSERC postdoctoral fellow in the Department of Electrical and Computer Engineering, University of Toronto, Toronto, Ontario, Canada. His postdoctoral work includes the design of the next generation FPGA in collaboration with Fujitsu research labs in Japan/USA.

Abstract

Field-Programmable Gate Arrays (FPGAs) are premanufactured Silicon devices that can be programmed to realize any digital circuit or system. FPGAs exhibit several advantages over Application Specific Integrated Circuit (ASIC) technologies such as standard cells. ASICs are typically fabricated in months and cost millions of dollars. However, FPGAs are programmed/reprogrammed in few seconds and cost hundreds of dollars. The programmability feature of FPGAs comes at the expense of extra area, delay, and power consumption. Typically, FPGAs occupy larger area and dissipate more switching power than ASIC standard cells by factors of 20-30X and 10X, respectively. In addition, FPGAs provide lower performance than ASIC standard cells by a factor of 4X. These drawbacks of FPGAs compared to ASIC standard cells are due to the configurable routing fabric that trades area, power, and performance to achieve the programmability feature. The biggest design question is always whether to use FPGA or ASIC? There are significant opportunities in the next generation FPGA design such as Embedded NoC (Network on Chip) based FPGA, low power FPGA, PDR (Partial Dynamic Reconfiguration) capability, asynchronous FPGA, nano-scale devices integration, PVT and reliability aware FPGA design, and 3D FPGA. The objective of this talk is to survey briefly how distinct design techniques and methods at different abstraction levels (i.e., device, circuit, CAD, and architecture) are impacted by, and successfully responding to, these FPGA design challenges.