alexa A Novel Approach for Generating Test Patterns Using AL
ISSN ONLINE(2278-8875) PRINT (2320-3765)

International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering
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Special Issue Article

A Novel Approach for Generating Test Patterns Using ALU

S.Selvi and M.Thangamani
Assistant Professor, M. Kumarasamy College of Engineering, Karur, India
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Abstract

The increase of the Integrated Circuit (IC) capabilities offers the designer the possibility to include more complex functionality into it. Processors are one of the general purpose modules found in these complex circuits which can be reused for test. It has been shown that processors can reach similar levels of Fault Coverage (FC) to LFSR, by looping arithmetic operations. Weighted pseudorandom techniques have also been used to improve the fault coverage. These weighted pseudorandom techniques result in low testing time and power. Generation of test vectors using arithmetic functions is becoming an attractive solution due to possibility of reusing internal arithmetic data paths of system cores for testing purposes. It requires neither additional IC area nor special bus to transmit test vectors; these can be sent by standard address or data buses to the Modules Under Test (MUT). Of the four basic arithmetic operations that are available in processors, addition has the most advantages: it is usually implemented by hardware, and it is more energy and time efficient. Also, if the buses require the The increase of the Integrated Circuit (IC) capabilities offers the designer the possibility to include more complex functionality into it. Processors are one of the general purpose modules found in these complex circuits which can be reused for test. It has been shown that processors can reach similar levels of Fault Coverage (FC) to LFSR, by looping arithmetic operations. Weighted pseudorandom techniques have also been used to improve the fault coverage. These weighted pseudorandom techniques result in low testing time and power. Generation of test vectors using arithmetic functions is becoming an attractive solution due to possibility of reusing internal arithmetic data paths of system cores for testing purposes. It requires neither additional IC area nor special bus to transmit test vectors; these can be sent by standard address or data buses to the Modules Under Test (MUT). Of the four basic arithmetic operations that are available in processors, addition has the most advantages: it is usually implemented by hardware, and it is more energy and time efficient. Also, if the buses require thetransmission of the test vector by pieces, it can be split into smaller operations by propagating the carry signal. This project proposes a method for designing a low power and area efficient test pattern generator (TPG) using ALU. The TPG is designed using a newly proposed Carry Select Adder in place of the binary adders in ALU. This helps to achieve low power consumption , low area and less speed too than the earlier designs.

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