alexa A Novel Approach to Implement a High Speed and Low Mem
ISSN ONLINE(2278-8875) PRINT (2320-3765)

International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering
Open Access

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Research Article

A Novel Approach to Implement a High Speed and Low Memory Separable 2D DWT Architecture

N.A.Raju Desamsetti1 and G.Sita Annapurna2
  1. M.Tech(Scholar), Dept. of ECE, Sri Vasavi Institute of Engineering and Technology, Nandamuru, AP, India
  2. Assistant Professor, Dept. of ECE, Sri Vasavi Institute of Engineering and Technology, Nandamuru, AP, India
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Abstract

The basic idea behind wavelets is to analyze according to scale. Indeed, some researchers in the wavelet field feel that, by using wavelets, one is adopting a perspective in processing data. Wavelets are functions that satisfy certain mathematical requirements and are used in representing data or other functions. In this paper, separable pipeline architecture for fast computation of the 2D DWT with a less memory and low latency is proposed. The low latency and less memory is achieved by proper designing of two 1-D DWT filtering processes and also efficiently transferring the data between the two 1-D DWT filters. The functionality of the architecture is verified through modelsim simulator and the synthesis is performed using XILINX ISE.

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