alexa Design and Implementation of High Performance Parallel
ISSN ONLINE(2320-9801) PRINT (2320-9798)

International Journal of Innovative Research in Computer and Communication Engineering
Open Access

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Research Article

Design and Implementation of High Performance Parallel Prefix Adders

CH.Sudha Rani, CH.Ramesh
  1. Student, Department of ECE, Ganapathy Engineering College, Warangal, India.
  2. Associate Professor, Department of ECE, Ganapathy Engineering College, Warangal, India
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Abstract

performance High performance adders (also known as carry tree or parallel prefix adders) areknown to have the best in VLSI designs. However, this performance advantage does not translate directly into FPGA implementations due to constraints on logic block configurations and routing overhead. This paper investigates four types of carry-tree adders (the Kogge-Stone, sparse Kogge-Stone, spanning tree adder and Brent-kung adder) and compares them to the simple Ripple Carry Adder (RCA) and Carry Skip Adder (CSA). These designs of varied bitwidths were implemented on a Xilinx Spartan 3E FPGA and delay measurements were made with a high-performance logic analyzer. Due to the presence of a fast carry-chain, the RCA designs exhibit better delay performance up to 128 bits. The carry-tree adders are expected to have a speed advantage over the RCA as bit widths approach 256.

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